I was curious to find out how fast the interrupt response of a STM32H743 can be. I connected a simple square wave generator to Pin PG3 of my old NUCLEOH743ZI-Board. A PWM output of my raspberry Pi PICO was used as a square wave generator Read More …
Autor: DM1CR
How to connect an ADC3660 to an MCU (part II)
The following timing diagram (that I draw with Wavedrom, a fantastic tool for that purpose) shows in the upper part the output format of the ADC3660 as I understand it from the datasheet: The signal in the middle („NSS_TI“) shows the NSS signal as it Read More …
How to connect an ADC3660 to an MCU (part I)
TI’s new family of SAR-ADCs with integrated DDCs could be a game changer for building SDRs for HAM radio operators. Why? Because these ADCs do not only contain an NCO and a complex digital IQ downmixer, they also integrate a decimation stage and an output Read More …
SI5351A and frequency counting with the STM32H743
I wanted to play around with the SI5351A clock generator, but for verifying the output frequencies of the SI5351 I thought it would be great to have a frequency counter at hand. Unfortunately I do not own a frequency counter, so I looked for some Read More …
H7 ADC revisited (Bandpass sampling and analog bandwidth of the 16-bit ADC peripheral of the STM32H7, Part IV)
The question that interested me was: How strongly does the SNR of the ADC-peripheral of the H7 depend on the chosen clock source? Unfortunately, neither the H7 datasheets nor application notes like AN5354 treat this topic. The FFT plot shown in figure 1 of AN5354 Read More …
NUCLEO-H743ZI vs. NUCLEO-H743ZI2 and STLINK V3 vs. STLINK V2
I wanted to try out one of the newer NUCLEO-H743ZI2 boards, because they are populated with MCUs with the newer mask revision V. In mask revision V, ST changed the clocking scheme of the ADC. This new clocking scheme is interesting and I wanted to Read More …
H7 ADC revisited (Bandpass sampling and analog bandwidth of the 16-bit ADC peripheral of the STM32H7, Part III)
Summary: It is shown that the shape of the transfer function and of the SNR of the internal ADC of the STM32H7 vs. frequency of the applied signal can be explained with a very simple simulation model up to quite high signal frequencies. The PLL Read More …
Improved Reception of Radio DARC; preamp unnecessary
CIC compensation filters now follow the 2-stage decimating CIC filters for the I-Q-signals. The CIC compensation filters are two identical FIR filters (one filter each for the I signal and an identical filter for the Q signal) with currently 81 taps. They flatten the passbands Read More …
The DFSDM of the STM32H7 or 128 != 16×8 != 8×16 (Part III)
continued from part II: The passband of CIC filters is not flat. This begs the question of whether this behavior should be corrected. In most cases, the CIC is therefore followed by a so-called CIC compensation filter. Zooming into the filter plot of the sinc4/dec.15 Read More …
The DFSDM of the STM32H7 or 128 != 16×8 != 8×16 (Part II)
continued from part I: As explained in part I, the first version of my H7-SDR uses only one CIC filter of the DSFDM for filtering the I-signal and another one for filtering the Q-signal. However, the DSFDM contains 4 filters (see chapter 30 of RM0433 Read More …